1. Field of the Invention
This invention relates generally to digital driver circuits and, in particular, to a digital driver circuit for controlling the operation of an EML (electroabsorption modulated laser) or a direct modulated laser.
2. Description of the Related Art
An important feature of the digital driver is its output capability and efficiency, that is, the maximum voltage amplitude the driver can apply across a load (in, for example, an EML) or the maximum current through the load (in, for example, a laser) for a given power supply voltage. In order to reduce the unavoidable power dissipation in a driver circuit, the power supply voltage is reduced. This is the observed long-term trend for systems with progressing miniaturization: the subcomponents move closer together and there overall power dissipation is reduced due to an ongoing power supply voltage reduction. A driver is more efficient if the output capability is constant with its reduced supply voltage.
The last power stage in a digital driver is generally an emitter-coupled current switching transistor pair fed by a current source. The adjustable current source, normally a single transistor guarantees constant amplitude output current as shown in Chen & Bosch, GaAs MESFET Laser-Driver IC for 1.7 Gbits/s Lightwave Transmitter, in Journal of Lightwave Technology, Vol. 6, No. 3, Mar. 3, 1988 and Shumate et al., GaAiAs Laser Transmitter for Lightwave Transmission Systems, in The Bell Systems Technical Journal, July-August 1978, which are hereby incorporated by reference.
With proper bias levels the transistors are never driven into saturation which results in fast switching times. Another feature of these circuits is the constant current nature generating minimum switching noise on the power bus.
FIG. 1 illustrates a conventional driver circuit 10 used to control a modulated device 50 such as a laser or EML. The circuit 10 includes three stages, an input stage 12, level shifting stage 30 and an output stage 40.
The input stage 12 contains two load resistors 14, 16, and first, second and third transistors 18, 20, 22. The first transistor 18 has its gate terminal connected to the input data signal DATA while the second transistor 20 has its gate terminal connected to the complement of the input data signal DATA. The first load resistor 14 is connected between a power supply potential V.sub.CC and the drain terminal of the first transistor 18. The second load resistor 16 is connected between the power supply potential V.sub.CC and the drain terminal of the second transistor 20. The first and second transistors 18, 20 have their source terminals connected to the drain terminal of the third transistor 22. The third transistor 22 has its source terminal connected to a second potential V.sub.EE and its gate terminal connected to a gate voltage V.sub.G sufficient to activate the transistor 22. The power supply potential V.sub.CC is usually 0 volts while the second potential V.sub.EE is usually -5 volts.
The input stage 12 quantizes the input signals DATA, DATA and they appear shifted to a more positive potential at the load resistors 14 and 16. After this processing the signals are shifted to a more negative potential through the level shifter stage 30 to ensure the proper potential level for the final driver stage 40. The level shifting stage 30 consists of two individual level shifter circuits 32, 34. The outputs of the two level shifter circuits 32, 34 are fed into the output stage 40.
The output stage 40 includes a third load resistor 48 and fourth, fifth and sixth transistors 42, 44, 46. The fourth transistor 42 has its gate terminal connected to the level shifted input data signal while the fifth transistor 44 has its gate terminal connected to the level shifted complement of the input data signal. The third load resistor 48 is connected between the power supply potential V.sub.CC and the drain terminal of the fourth transistor 42. The fourth and fifth transistors 42, 44 have their source terminals connected to the drain terminal of the sixth transistor 46. The sixth transistor 46 has its source terminal connected to the second potential V.sub.EE and its gate terminal connected to a control voltage V.sub.C1 which is sufficient to activate the transistor 46. In this configuration, the fourth and fifth transistors 42, 44 form a differential amplifier circuit 45 whose current is controlled by the sixth transistor 46 (acting as a current source transistor). The output of the differential amplifier circuit 45 drives the modulated device 50. That is, the differential amplifier circuit 45 switches the constant source current of the device 46 according to the input signals DATA, DATA and creates an output with constant current and constant voltage amplitudes at device 50.
Although the conventional driver circuit 10 works well in many applications, it has an insufficient drive capability for some applications with a given supply voltage.
In order for the circuit 10 to work safely, the common emitter potential of switching devices 42 and 44 must be sufficiently positive relative to VEE so that the current source transistor 46 is never driven into saturation. One also has to take into consideration variations in power supply voltages VCC-VEE and voltage drop differences on level shifters 32 and 34 and gate-emitter voltage differences on devices 42 and 44 from lot to lot and with temperature. As a result the gate voltages of devices 42 and 44 must be overdesigned to set an ample safety margin relative to VEE with the result that the maximum output drive voltage amplitude is about two volts less than the supply voltage VCC-VEE. This voltage amplitude limit is also limiting the maximum current, which can be drawn through a laser with a matching resistor in series.
There is a need and desire for increased output current and voltage amplitudes in a digital driver circuit used to drive a laser or EML respectively, which has fewer problems caused by a shortage of voltage for operating transistors in the output stage.